Path: OKDatasheet > Semiconductor Datasheet > Lattice Datasheet > M5LV-512/120-20HI
M5LV-512/120-20HI manual: 20ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-512/120-20HI Similar
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- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10VI
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10YC
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10YI
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- M5LV-128/104-12VC
- 12ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-12VI
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-12YI
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-15VI
- 15ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-512/120-20HI Datasheet and M5LV-512/120-20HI manual
Manufacturer : Lattice
Packing : PQFP
Pins : 100
Temperature : Min -40 °C | Max 85 °C
Size : 1126 KB
Application : 20ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-512/120-20HI PDF Download