Path: OKDatasheet > Semiconductor Datasheet > Lattice Datasheet > M5LV-256/120-7YC
M5LV-256/120-7YC manual: 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-256/120-7YC Similar
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M5LV-256/120-7YC Datasheet and M5LV-256/120-7YC manual
Manufacturer : Lattice
Packing : PQFP
Pins : 100
Temperature : Min 0 °C | Max 70 °C
Size : 1126 KB
Application : 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-256/120-7YC PDF Download