Path: OKDatasheet > Semiconductor Datasheet > Lattice Datasheet > M5LV-128/68-12VI
M5LV-128/68-12VI manual: 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-128/68-12VI Similar
- M5LV-128/104-10VC
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10VI
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10YC
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-10YI
- 15ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-12VC
- 12ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-12VI
- 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
- M5LV-128/104-12YI
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- M5LV-128/104-15VI
- 15ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-128/68-12VI Datasheet and M5LV-128/68-12VI manual
Manufacturer : Lattice
Packing : TQFP
Pins : 100
Temperature : Min -40 °C | Max 85 °C
Size : 1126 KB
Application : 10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-128/68-12VI PDF Download