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PLSI3256-50LG manual: High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 57MHz
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PLSI3256-50LG Datasheet and PLSI3256-50LG manual
Manufacturer : Lattice
Packing : CPGA
Pins : 167
Temperature : Min 0 °C | Max 70 °C
Size : 1126 KB
Application : High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 57MHz
PLSI3256-50LG PDF Download